The present invention relates to a high voltage semiconductor device. More particularly, the present invention relates to a vertical semiconductor device and a method of manufacturing the same.
FIG. 34 is a cross-sectional view showing a high voltage MOSFET disclosed in U.S. Pat. No. 5,216,275. The structure of this high voltage MOSFET 300 is described below. The high voltage MOSFET 300 is a vertical MOSFET. The high voltage MOSFET 300 is formed on a semiconductor substrate. The semiconductor substrate includes an n+-type drain region 304. p-type semiconductor regions 302 and n-type semiconductor regions 301 are formed on the drain region 304, arranged alternately p+-type semiconductor regions 303 are formed on the p-type semiconductor regions 302. The end sections of the p+-type semiconductor regions 303 are located on the n-type semiconductor regions 301. A gate electrode 309 is formed on the n-type semiconductor region 301 and the sidewalls of the p+-type semiconductor regions 303 through a gate insulating film 308. A pair of n+-type source regions 305 is formed on the surfaces of the p+-type semiconductor regions 303 with an interval therebetween. Source electrodes 310 are formed on the p+-type semiconductor regions 303 between the n+-type source regions 305.
The operation of the high voltage MOSFET 300 is described below. The operation in the case where the high voltage MOSFET 300 is in an ON state is described first. When a positive voltage is applied to the gate electrode 309, channel regions are formed in the p+-type semiconductor regions 303 in regions facing the gate insulating film 308. Electrons are supplied from the source regions 305 and reach the drain region 304 through the channel regions and the n-type semiconductor region 301. In this case, the ON voltage of the high voltage MOSFET 300 is mainly determined by a voltage drop by the resistance of the n-type semiconductor region 301.
The operation in the case where the high voltage MOSFET 300 is in an OFF state is described below. Either 0 V or a negative voltage is applied to the gate electrode 309. This causes the channel regions to disappear. In the case where the drain voltage is about 10 V, depletion layer is formed and spread along junctions formed between the n-type semiconductor region (drain region 304 and n-type semiconductor region 301 make up the n-type semiconductor region) and the p-type semiconductor regions (p-type semiconductor regions 302 and p+-type semiconductor regions 303 make up the p-type semiconductor regions). The widths of the n-type semiconductor region 301 and the p-type semiconductor region 302 are small. Therefore, the n-type semiconductor region 301 and the p-type semiconductor regions 302 are depleted completely as the drain voltage increases. Specifically, the breakdown voltage is sustained by the structural section in which the n-type semiconductor regions 301 and the p-type semiconductor regions 302 are arranged alternately.
The above U.S. Patent describes the high voltage MOSFET having the structural section in which the n-type semiconductor regions 301 and the p-type semiconductor regions 302 are arranged alternately as a device with a high breakdown voltage and a low ON voltage.
The method of forming the p-type semiconductor regions 302 and the n-type semiconductor regions 301 of the high voltage MOSFET 300 shown in FIG. 34 is described below. An n-type (or p-type) epitaxial layer is epitaxially grown on the semiconductor substrate which becomes the drain region 304. The n-type (or p-type) epitaxial layer is selectively removed, thereby forming trenches which reach the drain region 304. The remaining n-type (or p-type) epitaxial layer becomes the n-type semiconductor regions 301 (or p-type semiconductor regions 302). The trenches are filled with the p-type semiconductor regions 302 (or n-type semiconductor regions 301) by epitaxial growth.
As described above, the structural section in which the p-type semiconductor regions 302 and the n-type semiconductor regions 301 are arranged alternately is fabricated by forming the trenches by selectively removing the semiconductor layer of first conductive type and filling the trenches with the semiconductor layers of second conductive type by epitaxial growth. The epitaxial growth step is generally a high temperature process. Therefore, in the case of fabricating the structural section in which the p-type semiconductor regions and the n-type semiconductor regions are arranged alternately using the above method, phenomena may occur in which impurities in the semiconductor layers of second conductive type are diffused into the semiconductor layers of first conductive type and impurities in the semiconductor layers of first conductive type are diffused into the semiconductor layers of second conductive type during the formation of the semiconductor layers of second conductive type. Therefore, it is difficult to miniaturize the structural section in which the p-type semiconductor regions and the n-type semiconductor regions are formed, arranged alternately.
The present invention has been attained to solve the above problems. An objective of the present invention is to provide a vertical semiconductor device including a structural section in which a first semiconductor region of first conductive type and a second semiconductor region of second conductive type are arranged alternately without filling trenches by epitaxial growth, and a method of manufacturing the same.
The present invention relates to a vertical semiconductor device including a structural section in which a first semiconductor region of first conductive type and a second semiconductor region of second conductive type are arranged alternately,
wherein a breakdown voltage is sustained by the structural section,
wherein a graded junction is formed between the first semiconductor region and the second semiconductor region, and
wherein an impurity profile of first conductive type in the graded junction is graded along a direction in which the first and second semiconductor regions are arranged alternately.
According to the vertical semiconductor device of the present invention, since the distribution of the impurities of first conductive type is graded in the first semiconductor region, depletion layer can be spread widely in a region in which the concentration of the impurities of first conductive type is lower. Therefore, the first semiconductor region and the second semiconductor region can be easily depleted even if the widths of these regions are comparatively greater, whereby an increase in the breakdown voltage can be realized.
The vertical semiconductor device including the above structural section has a high breakdown voltage and a low ON voltage. The reasons there for are described below taking a high voltage vertical MOS field effect transistor as an example. The breakdown voltage is an important parameter which determines the performance of the transistor. In the case where a section corresponding to the structural section formed of only the first semiconductor region of first conductive type, the breakdown voltage is determined by the junction breakdown voltage at the junction between the first semiconductor region and a second conductive type body region (channel is formed in body region). The junction breakdown voltage increases as the impurity concentration in the first semiconductor region decreases. This is because the length of the depletion layer increases as the impurity concentration decreases. The length of the depletion layer refers to the length of the depletion layer in a source-drain direction. However, the resistance of the first semiconductor region increases as the impurity concentration decreases. This causes the ON voltage of the transistor to be increased. In the transistor having such a structure, since the impurity concentration in the first semiconductor region is determined by the breakdown voltage, it is difficult to decrease the ON voltage in the case of a high voltage transistor.
In the case of a transistor having the above structural section, the depletion layer is spread from the junction between the first semiconductor region and the second semiconductor region toward the first semiconductor region and the second semiconductor region. Therefore, the structural section can be depleted completely even if the impurity concentration in the first semiconductor region is increased. Specifically, the breakdown voltage can be increased while decreasing the ON voltage.
As examples of the vertical semiconductor device according to the present invention, MOS field effect transistors can be given. A UMOS and VMOS are given as such MOS field effect transistors.
The vertical semiconductor device according to the present invention may have the following feature:
The distribution of the impurities of first conductive type in the graded junction decreases toward a junction between the first semiconductor region and the second semiconductor region.
When a voltage is applied to the junction (pn junction, for example), the electric field strength generally reaches a maximum at the junction. The lower the impurity concentration, the lower the electric field strength at the same applied voltage. Therefore, the junction breakdown voltage increases. According to this feature, the junction breakdown voltage at the junction can be increased.
The vertical semiconductor device according to the present invention may have the following feature:
A trench is formed in the first semiconductor region, and the distribution of the impurities of first conductive type increases from the junction toward the trench.
According to this feature, the resistance of the first semiconductor region decreases near the trench. Therefore, a large amount of current can be caused to flow through the first semiconductor region near the trench. Moreover, in the case of forming a buried electrode in the trench, current can be quickly cut off.
The vertical semiconductor device according to the present invention may have the following feature:
The vertical semiconductor device comprises a semiconductor layer of second conductive type, another trench, and a buried gate electrode,
the other trench is located in the semiconductor layer,
the other trench is located over the trench, and
the buried gate electrode is located in the other trench.
The vertical semiconductor device according to the present invention may have the following feature:
The buried gate electrode extends to the trench.
According to this vertical semiconductor device, since an accumulation layer can be formed in the first semiconductor region near the trench, the ON voltage can be further decreased. The accumulation layer refers to a layer containing a large number of first conductive type carriers formed in the first conductive type semiconductor region by the gate effects of a MIS structure. Since the resistance of the accumulation layer is smaller than that of the first semiconductor region, the ON voltage can be decreased.
The vertical semiconductor device according to the present invention may have the following feature:
The vertical semiconductor device comprise a planar gate electrode.
The vertical semiconductor device according to the present invention may have the following feature:
The graded junction comprise a one-sided abrupt junction.
The vertical semiconductor device according to the present invention may have the following feature:
A width of the other trench is substantially uniform.
The vertical semiconductor device according to the present invention may have the following feature:
A width of the other trench becomes smaller towards a direction of a bottom thereof.
The vertical semiconductor device according to the present invention may have the following feature:
The vertical semiconductor device comprise a third semiconductor region of first conductive type which becomes a drain and a fourth semiconductor region of first conductive type which becomes a source, and
the structural section is located between the third semiconductor region and the fourth semiconductor region.
The vertical semiconductor device according to the present invention may have the following feature:
The vertical semiconductor device comprise a third semiconductor region of first conductive type which becomes a drain,
the structural section is located over the third semiconductor region, and
the trench reaches the third semiconductor region through the first semiconductor region to remove part of a surface of the third semiconductor region.
According to this vertical semiconductor device, operation reliability of the vertical semiconductor device can be increased.
The present invention further relates to a method of manufacturing a vertical semiconductor device including a structural section in which a first semiconductor region of first conductive type and a second semiconductor region of second conductive type are arranged alternately,
wherein a breakdown voltage is sustained by the structural section, and
wherein the method comprises steps of:
(a) forming a trench in a semiconductor layer of second conductive type; and
(b) diffusing impurities of first conductive type into the semiconductor layer through a sidewall of the trench, then forming the first semiconductor region in part of the semiconductor layer and allowing a remaining portion of the semiconductor layer to become the second semiconductor region.
According to the method of manufacturing a vertical semiconductor device of the present invention, the first semiconductor region is formed by diffusion. Therefore, the first semiconductor region and the second semiconductor region have a graded junction structure. In this graded junction, the distribution of the impurities of first conductive type is graded along a direction in which the first semiconductor region and the second semiconductor region are arranged alternately.
According to the present invention, the first semiconductor region is formed by diffusion. Therefore, the structural section can be miniaturized in comparison with a method of filling the trench with the first semiconductor region by epitaxial growth. As a result, the degree of integration of the vertical semiconductor device can be increased.
The diffusion may be at least either vapor phase diffusion or solid phase diffusion, for example.
The method of manufacturing a vertical semiconductor device according to the present invention may have the following feature:
The method comprises a step of forming the semiconductor layer over a third semiconductor region of first conductive type which becomes a drain, before the step (a), and
in the step (a), the trench is formed so as to reach the third semiconductor region through the semiconductor layer to remove part of a surface of the third semiconductor region.
The method of manufacturing a vertical semiconductor device according to the present invention may have the following feature:
The diffusion comprises vapor phase diffusion in the step (b).
According to this method, impurities can be diffused into a small trench with a width of 0.5 xcexcm or less.
The method of manufacturing a vertical semiconductor device according to the present invention may have the following feature:
The method comprises a step of forming a film containing the impurities in the trench between the step (a) and the step (b), and
the impurities are diffused from the film containing the impurities by solid phase diffusion in the step (b).
Since it is easy to control the impurity concentration in the film containing the impurities which becomes a diffusion source, the impurity distribution in the first semiconductor region can be easily controlled.
In the case where the impurities of first conductive type are n to type, a PSG (Phosphorous Silicate Glass) film and phosphorus doped polysilicon (formed of PH3+SiH4 gas or PH3+Si2 H6 gas, for example) can be given as examples of the film containing the impurities. In the case where the impurities of first conductive type are p to type, BSG (Boron Silicate Glass) film and boron doped polysilicon (formed of B2H6+SiH4 gas or B2H6+Si2H6 gas, for example) can be given as examples of the film containing the impurities.
The method of manufacturing a vertical semiconductor device according to the present invention may have the following feature:
The method comprises a step of forming a thin film on the sidewall of the trench between the step (a) and the step (b), and
the impurities are diffused into the semiconductor layer through the thin film in the step (b).
According to this method, diffusion controllability can be increased. The reasons therefor are described below. If the impurities are diffused in a state in which no film is formed on the sidewall of the trench, the impurity concentration in the first semiconductor region is higher near the upper portion of the trench than near the lower portion of the trench. This is because a greater amount of impurities is supplied from the upper portion of the trench than the lower portion of the trench (supply-limited).
In the case where the impurities are diffused through the thin film formed on the sidewall of the trench, the diffusion follows the diffusion limited which is a limited for impurities diffused through the thin film rather than the supply-limited. Therefore, according to this method, the impurity concentration can be made uniform along the sidewall of the trench.
The thickness of the thin film is 5 nm to 50 nm, for example. If the thickness of the thin film is 5 nm or more, it is unnecessary to diffuse the impurities at a low temperature (800xc2x0 C. or less, for example) that decreases diffusion controllability. If the thickness is 50 nm or less, the impurities can be diffused even if the temperature is extremely high (1000xc2x0 C. or more., for example). As examples of the thin film, a silicon oxide film can be given.
The method of manufacturing a vertical semiconductor device according to the present invention may have the following feature:
The method comprises a step of forming a planar gate electrode over an upper surface of the semiconductor layer after the step (b).
The method of manufacturing a vertical semiconductor device according to the present invention may have the following feature:
The method comprises, after the step (b):
a step of forming another trench in the semiconductor layer; and
a step of forming a buried gate electrode in the other. trench.
The method of manufacturing a vertical semiconductor device according to the present invention may have the following feature:
The method comprises, before the step (a):
a step of forming another trench in the semiconductor layer; and
a step of forming a buried gate electrode in the other trench, and
the trench is formed through the buried gate electrode in the step (a).
According to this method, the trench can be formed right under the other trench. Therefore, the degree of integration of the vertical semiconductor device can be increased in comparison with a case of forming the trench so as not to overlap with the other trench on a plane. According to this method, the width of the trench is smaller than that of the other trench.
The method of manufacturing a vertical semiconductor device according to the present invention may have the following feature:
The method may comprise a step of forming another trench in the semiconductor layer before the step (a),
a width of the other trench becomes smaller towards a direction of a bottom thereof, and
the trench is formed from the bottom of the other trench in the step (a).
According to this method, the trench can be formed right under the other trench.
The method of manufacturing a vertical semiconductor device according to the present invention may have the following feature:
The method comprises, before the step (a):
a step of forming another semiconductor layer of second conductive type over the semiconductor layer; and
a step of forming another trench in the other semiconductor layer, and
the trench is continuously formed with the other trench in the step (a).
The method of manufacturing a vertical semiconductor device according to the present invention may have the following feature:
The method comprises a step of forming a thin film on the sidewall of the trench between the step (a) and the step (b), and
the impurities are diffused into the semiconductor layer through the thin film in the step (b).
The method of manufacturing a vertical semiconductor device according to the present invention may have the following feature:
The method comprises a step of forming a film containing. the impurities in the trench and the other trench after the step of forming the thin film, and
the impurities are diffused from the film containing the impurities by solid phase diffusion in the step (b).
The method of manufacturing a vertical semiconductor device according to the present invention may have the following feature:
The method comprises, after the step (b):
a step of removing the thin film;
a step of forming another thin film including a gate insulating film over the sidewall of the trench and a sidewall of the other trench; and
a step of forming a buried electrode layer including a gate electrode in the trench and the other trench.
In the vertical semiconductor device manufactured by this method, an accumulation layer can be formed in the first semiconductor region by the buried electrode layer.
The method of manufacturing a vertical semiconductor device according to the present invention may have the following feature:
The method comprises, after the step (b):
a step of removing the film containing the impurities and the thin film;
a step of forming another thin film including a gate insulating film on the sidewall of the trench and a sidewall of the other trench; and
a step of forming a buried electrode layer including a gate electrode in the trench and the other trench.
The method of manufacturing a vertical semiconductor device according to the present invention may have the following feature:
The method comprises:
a step of forming the semiconductor layer over a third semiconductor region of first conductive type which becomes a drain, before the step (a); and
a step of forming a fourth semiconductor region of first conductive type which becomes a drain in the semiconductor layer, after the step (b).